Name
Abstract | ||
|---|---|---|
A 10b 205MS/S 1mm2 ADC for flat-panel display applications is implemented in a 90nm CMOS process. The ADC with an LDO regulator achieves a 53dB PSRR for a 100MHz noise tone and a 55.2dB SNDR for a 30MHz 1Vpp single-ended input at 205MS/S. The core ADC power consumption is 40mW from a 1V non-regulated supply. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ISSCC.2007.373492 | ISSCC |
Keywords | Field | DocType |
cmos process,flat-panel display applications,90 nm,1 v,analogue-digital conversion,40 mw,30 mhz,cmos digital integrated circuits,10 bit,ldo regulator,flat panel displays,pipeline analog-to-digital converter,100 mhz | Noise measurement,Computer science,CMOS,Electronic engineering,Switched capacitor,Power supply rejection ratio,Flat panel display,Electrical engineering,Low-dropout regulator,Voltage regulator,Amplifier | Conference |
ISSN | ISBN | Citations |
0193-6530 E-ISBN : 1-4244-0853-9 | 1-4244-0853-9 | 25 |
PageRank | References | Authors |
2.71 | 5 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seung-Chul Lee | 1 | 124 | 18.27 |
| Young-Deuk Jeon | 2 | 98 | 13.50 |
| Kwi-Dong Kim | 3 | 70 | 10.44 |
| Jong-Kee Kwon | 4 | 158 | 23.10 |
| Jongdae Kim | 5 | 102 | 17.00 |
| Jeong-Woong Moon | 6 | 25 | 2.71 |
| Woo-Yol Lee | 7 | 25 | 3.05 |