Name
Title | ||
|---|---|---|
A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm. |
Abstract | ||
|---|---|---|
This paper presents a low-power decision-feedback equalizer (DFE) receiver front-end and a two-step minimum bit-error-rate (BER) adaptation algorithm. A high energy efficiency of 0.46 mW/Gbps is made possible by the combination of a direct-feedback finite-impulse-response (FIR) DFE, an infinite-impulse-response (IIR) DFE, and a clock-and-data recovery (CDR) circuit with adjustable timing offsets. ... |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/JSSC.2013.2274904 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Decision feedback equalizers,Receivers,Finite impulse response filters,Timing,Clocks,Bit error rate | Computer science,Control theory,Infinite impulse response,Voltage,Algorithm,Communication channel,Stochastic process,Electronic engineering,CMOS,Finite impulse response,Bit error rate,Low-power electronics | Journal |
Volume | Issue | ISSN |
48 | 11 | 0018-9200 |
Citations | PageRank | References |
5 | 0.61 | 11 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seuk Son | 1 | 11 | 2.98 |
| HanSeok Kim | 2 | 79 | 6.85 |
| Myeong-Jae Park | 3 | 42 | 5.77 |
| Kyung-Hoon Kim | 4 | 55 | 8.68 |
| E.-Hung Chen | 5 | 93 | 9.14 |
| Brian S. Leibowitz | 6 | 100 | 12.89 |
| Jaeha Kim | 7 | 382 | 51.63 |