Title | ||
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On the tradeoff between node degree and communication channel width in shuffle-exchange networks |
Abstract | ||
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The architecture of direct connected multiprocessor using the K-ary shuffle-exchange topology is investigated in the presence of node pin-out constraints. These constraints translate into a tradeoff between node degree and width of the communication channels between nodes. A higher order shuffle uses a higher node degree to reduce inter-node distances, but it also results in a lower bandwidth per channel by decreasing its width. A generalization of the K-ary shuffle exchange architecture to non-power-of-K system sizes permits the study of this tradeoff at a fine level, for values of K=2, 3, 4, . . . This study points out that the tradeoff is more complex here than in the family of multidimensional meshes. Very low order shuffles (K<0.5 log2 N) do not perform well in any of the situations investigated. Among higher order shuffles, the best structure depends upon both the system size and the pin-out constraint, and monotonic reduction in message delays is not guaranteed as the order of the shuffle is increased |
Year | DOI | Venue |
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1991 | 10.1109/SPDP.1991.218289 | Dallas, TX |
Keywords | DocType | ISBN |
communication channels,higher order,multidimensional systems,network topology,switches,computer architecture,computer networks,intelligent networks | Conference | 0-8186-2310-1 |
Citations | PageRank | References |
2 | 0.37 | 8 |
Authors | ||
1 |
Name | Order | Citations | PageRank |
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Krishnan Padmanabhan | 1 | 305 | 33.55 |