Title
The algorithm of 16-bit scrambler in parallel for PCI express
Abstract
This paper describes an implementation and analysis of scrambler/descrambler for Physical layer of PCI Express device. When a binary bit stream being a high frequency of bit transition, electromagnetic interference (EMI) may be generated. These EMI noise is significant to PCI Express transmission line having 2.5Gbps bit stream. By scrambling the transmitted data, repetitive patterns can be eliminated so EMI noise removed. PCI Express uses Linear Feedback Shift Registers (LFSR) to scramble the data. This paper proposes the 16-bit parallel scrambler algorithm. Parallel scrambler/descrambler have precalculators that can get the value to be used as input value of LFSR in next state.
Year
Venue
Keywords
2005
Seventh IASTED International Conference on Signal and Image Processing
scramble(r),de-scramble(r),PCI express,Linear Feedback Shift Register (LFSR)
Field
DocType
Citations 
Computer science,Scrambler,16-bit,PCI Express,Computer hardware
Conference
0
PageRank 
References 
Authors
0.34
1
4
Name
Order
Citations
PageRank
Won-ok Kwon181.54
Kyoung Park200.68
Myung-Joon Kim34635.21
Hyuk-je Kwon400.68