Name
Abstract | ||
|---|---|---|
This article provides an overview of several logic redundancy schemes, including von Neumann's multiplexing logic, N-tuple modular redundancy, and interwoven redundant logic. We discuss several important concepts for redundant nanoelectronic system designs based on recent results. First, we use Markov chain models to describe the error-correcting and stationary characteristics of multiple-stage multiplexing systems. Second, we show how to obtain the fundamental error bounds by using bifurcation analysis based on probabilistic models of unreliable gates. Third, we describe the notion of random interwoven redundancy. Finally, we compare the reliabilities of quadded and random interwoven structures by using a simulation-based approach. We observe that the deeper a circuit's logical depth, the more fault-tolerant the circuit tends to be for a fixed number of faults. For a constant gate failure rate, a circuit's reliability tends to reach a stationary state as its logical depth increases. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/MDT.2005.97 | IEEE Design & Test of Computers |
Keywords | Field | DocType |
circuit reliability,random interwoven redundancy,probabilistic models,n-tuple modular redundancy,bifurcation,integrated circuit testing,integrated circuit reliability,n-tuple modular redundancy (nmr),nanotechnology,markov chain model,von neumann multiplexing logic,multiplexing,interwoven redundant logic,fault tolerance,failure rate,error bounds,error-correction,von neumann,redundancy,markov chain,system reliability,classical fault-tolerant approach,hardware redundancy,logic redundancy scheme,multiplexing logic,bifurcation analysis,fault-tolerance,fault-tolerant logic,logic gates,markov processes,nanoelectronics,logic redundancy,logic testing,error correction,probabilistic model,fault tolerant,system design,stationary state | Logic gate,Markov process,Computer science,Theoretical computer science,Electronic engineering,Redundancy (engineering),Fault tolerance,Probabilistic logic,Logical depth,Computer engineering,Von Neumann architecture,Logic redundancy | Journal |
Volume | Issue | ISSN |
22 | 4 | 0740-7475 |
Citations | PageRank | References |
69 | 3.83 | 3 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jie Han | 1 | 102 | 6.95 |
| Jianbo Gao | 2 | 287 | 34.63 |
| Yan Qi | 3 | 80 | 4.83 |
| Pieter Jonker | 4 | 390 | 49.20 |
| Jose A. B. Fortes | 5 | 446 | 52.01 |