Paper Info
Title
Inter-cluster communication in VLIW architectures
Abstract
The traditional VLIW (very long instruction word) architecture with a single register file does not scale up well to address growing performance demands on embedded media processors. However, splitting a VLIW processor in smaller clusters, which are comprised of function units fully connected to local register files, can significantly improve VLSI implementation characteristics of the processor, such as speed, energy consumption, and area. In our paper we reveal that achieving the best characteristics of a clustered VLIW requires a thorough selection of an Inter-cluster Communication (ICC) model, which is the way clustering is exposed in the Instruction Set Architecture. For our study we, first, define a taxonomy of ICC models including copy operations, dedicated issue slots, extended operands, extended results, and multicast. Evaluation of the execution time of the models requires both the dynamic cycle count and clock period. We developed an advanced instruction scheduler for all the five ICC models in order to quantify the dynamic cycle counts of our multimedia C benchmarks. To assess the clock period of the ICC models we designed and laid out VLIW datapaths using the RTL hardware descriptions derived from a deeply pipelined commercial TriMedia processor. In contrast to prior art, our research shows that fully distributed register file architectures (with eight clusters in our study) often underperform compared to moderately clustered machines with two or four clusters because of explosion of the cycle count overhead in the former. Among the evaluated ICC models, performance of the copy operation model, popular both in academia and industry, is severely limited by the copy operations hampering scheduling of regular operations in high ILP (instruction-level parallelism) code. The dedicated issue slots model combats this limitation by dedicating extra VLIW issue slots purely for ICC, reaching the highest 1.74 execution time speedup relative to the unicluster. Furthermore, our VLSI experiments show that the lowest area and energy consumption of 42 and 57% relative to the unicluster, respectively, are achieved by the extended operands model, which, nevertheless, provides higher performance than the copy operation model.
Year
DOI
Venue
2007
10.1145/1250727.1250731
TACO
Keywords
Field
DocType
instruction level parallelism,register file,functional unit,clock frequency,pipelining,instruction set architecture,media processor,optimizing compiler,instruction scheduling,vliw,register allocation,very long instruction word
Instruction-level parallelism,Computer architecture,Register allocation,Computer science,Instruction set,Very long instruction word,Parallel computing,Register file,Real-time computing,Clock rate,Speedup,TriMedia
Journal
Volume
Issue
ISSN
4
2
1544-3566
Citations 
PageRank 
References 
8
0.47
34
Authors
2
Name
Order
Citations
PageRank
Andrei Terechko11338.64
Henk Corporaal21787166.20