Name
Abstract | ||
|---|---|---|
This paper presents the latest results on a block turbo decoder design. We propose a block turbo decoder circuit for the error
protection of small data blocks such asAtm cells on anAwgn (additive white Gaussian noise) channel with a code rate close to 0.5. A prototype was developed atEnst Bretagne. It allowsBer (bit error rate) measurements down to 10−9 and uses programmable gate arrays (Fpga Xilinx circuits). The elementary extendedBch code and the data block size can be modified to fit specifications of different applications. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1007/BF02998582 | Annales des Télécommunications |
Keywords | Field | DocType |
prototype.,bch code,coder,block code,error correcting code,turbo code,decoder,additive white gaussian noise,block codes,bit error rate,product code,error correction code | Computer science,Block code,Turbo code,Block (data storage),Error detection and correction,Electronic engineering,Turbo equalizer,Soft-decision decoder,Decoding methods,Bit error rate | Journal |
Volume | Issue | Citations |
54 | 3 | 4 |
PageRank | References | Authors |
0.84 | 4 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Patrick Adde | 1 | 37 | 7.64 |
| Ramesh Pyndiah | 2 | 79 | 17.12 |
| Fabien Buda | 3 | 20 | 3.44 |