Paper Info
Title
Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations
Abstract
We investigate the feasibility of developing a comprehen- sive gate delay and slew models which incorporates output load, input edge slew, supply voltage, temperature, global process variations and local process variations all in the same model. We find that the standard polynomial mod- els cannot handle such a large heterogeneous set of input variables. We instead use neural networks, which are well known for their ability to approximate any arbitrary contin- uous function. Our initial experiments with a small subset of standard cell gates of an industrial 65nm library show promising results with error in mean less than 1% , error in standard deviation less than 3% and maximum error less than 11% as compared to SPICE for models covering 0.9- 1.1V of supply, -400C to 1250C of temperature, load, slew and global and local process parameters. Enhancing the conventional libraries to be voltage and temperature scal- able with similar accuracy requires on an average 4x more SPICE characterization runs.
Year
DOI
Venue
2008
10.1109/VLSI.2008.92
VLSI Design
Keywords
Field
DocType
slew model,standard polynomial mod,maximum error,standard cell gate,temperature scal,standard deviation,global process variation,intra-gate variations,local process variation,temperature scalable gate delay,local process parameter,input edge slew,neural nets,neural networks,continuous function
Polynomial,Spice,Computer science,Settling time,Voltage,Real-time computing,Electronic engineering,Standard cell,Artificial neural network,Standard deviation,Scalability
Conference
ISSN
ISBN
Citations 
1063-9667
0-7695-3083-4
2
PageRank 
References 
Authors
0.39
8
5
Name
Order
Citations
PageRank
Bishnu Prasad Das1112.06
vijay manikandan janakiraman220.39
Bharadwaj Amrutur345480.42
H. S. Jamadagni416030.14
N. V. Arvind5122.57