Paper Info
Title
Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure
Abstract
A large percentage of computed results have fewer significant bits compared to the full width of a register. We exploit this fact to pack multiple results into a single physical register to reduce the pressure on the register file in a superscalar processor. Two schemes for dynamically packing multiple "narrow-width" results into partitions within a single register are evaluated. The first scheme is conservative and allocates a full-width register for a computed result. If the computed result turns out to be narrow, the result is reallocated to partitions within a common register, freeing up the full-width register. The second scheme allocates register partitions based on a prediction of the width of the result and reallocates register partitions when the actual result width is higher than what was predicted. If the actual width is narrower than what was predicted, allocated partitions are freed up. A detailed evaluation of our schemes show that average IPC gains of up to 15% can be realized across the SPEC 2000 benchmarks on a somewhat register-constrained datapath.
Year
DOI
Venue
2004
10.1109/MICRO.2004.29
MICRO
Keywords
DocType
ISSN
actual width,exploiting narrow-width operands,multiple result,register packing,single physical register,register file pressure,common register,register file,computed result,full-width register,actual result width,full width,single register,parallel processing,pipelines,registers,compiler optimizations,enumeration,degradation,writing,availability
Conference
1072-4451
ISBN
Citations 
PageRank 
0-7695-2126-6
57
1.76
References 
Authors
32
4
Name
Order
Citations
PageRank
Oguz Ergin142425.84
Deniz Balkan21456.80
Kanad Ghose31220113.50
Dmitry Ponomarev489356.45