Name
Abstract | ||
|---|---|---|
In this paper, we propose new models for directly evaluating DPA leakage from logic information in CMOS circuits. These models are based on the transition probability for each gate, and are naturally applicable to various actual devices for simulating power analysis. We also report the effectiveness of the previously known enhanced DPA on our model. Furthermore, we demonstrate the weakness of previously known hardware countermeasures for both our model and FPGA and suggest secure conditions for the hardware countermeasure. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1007/11545262_27 | CHES |
Keywords | Field | DocType |
dpa leakage model,secure condition,hardware countermeasure,enhanced dpa,logic information,cmos logic circuit,new model,cmos circuit,dpa leakage,hardware countermeasures,transition probability,simulating power analysis,power analysis | Logic gate,Logic model,Telecommunications,Leakage (electronics),Computer science,Parallel computing,Field-programmable gate array,Circuit design,Electronic engineering,Combinational logic,CMOS,Electronic circuit | Conference |
Volume | ISSN | ISBN |
3659 | 0302-9743 | 3-540-28474-5 |
Citations | PageRank | References |
29 | 1.88 | 14 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daisuke Suzuki | 1 | 306 | 21.80 |
| Minoru Saeki | 2 | 243 | 14.88 |
| Tetsuya Ichikawa | 3 | 346 | 30.90 |