Name
Abstract | ||
|---|---|---|
We present a new approach to event-driven simu- lation that does not use a centralized run-time event queue, yet is capable of handling arbitrary models, including those with unclocked feedback and nonunit delay. The elimination of the event queue significantly reduces run-time overhead, resulting in faster simulation. We have implemented our algorithm in a pro- totype Verilog simulator called VeriSUIF. Using this simulator we demonstrate improved performance vs. a commercial simulator on a small set of programs. need for a run-time event queue and its associated overhead. We re- place the event queue with inexpensive run-time tests where necessary. For the models we have tested, these run-time tests incur significantly less overhead than a run-time event queue. We represent the event-driven behavior with an event graph, whose vertices represent events in the simulation and whose edges represent the causal relationships between the events. We apply the general technique of partial evaluation to schedule the events as well as pos- sible using statically available information. Specifically, the compiler tries to approximate the dynamic simulation process by keeping track of all the available static information that affects the contents of the run-time event queue in a dynamic simulation. This general method can be applied uniformly to all models, unlike previous approaches such as LECSIM (4), TORTLE (5) and (6). To test our algorithm, we have implemented a prototype simulator, called VeriSUIF, using the SUIF (Stanford University Intermediate Format) compiler system (7). We chose Verilog mainly because it is a relatively simple language to implement. The VeriSUIF simulator is particularly useful for long-running regression tests because it pro- duces a faster simulation than other techniques. However, our current implementation is unsuitable for other phases of the design process because it does not support interactive debugging. The remainder of the paper is organized as follows. First we give a brief overview of Verilog and describe the features of Verilog that we support. Then we describe the event graph representation which underlies our method. Next we describe our mathematical model of traditional event-driven simulation and our static simulation technique. Finally, we discuss some optimizations, experimental results, and our conclusions. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1145/217474.217522 | DAC |
Keywords | Field | DocType |
event-driven simulation,general method,design process,mathematical model,logic,computational modeling,graph representation,feedback,dynamic simulation,regression testing,discrete event simulation,testing,partial evaluation | Computer architecture simulator,Computer science,Queue,Real-time computing,Verilog,Small set,Hardware design languages,Discrete event simulation | Conference |
ISBN | Citations | PageRank |
0-89791-725-1 | 27 | 2.51 |
References | Authors | |
7 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Robert S. French | 1 | 82 | 24.18 |
| Monica S. Lam | 2 | 5585 | 705.61 |
| Jeremy R. Levitt | 3 | 203 | 22.85 |
| Kunle Olukotun | 4 | 4532 | 373.50 |