Name
Abstract | ||
|---|---|---|
SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to Single Event Upsets (SEUs). We show that a large portion (40%-60% for the circuits in our experiments) of the total used LUT configuration bits are don't care bits, and propose to decide the logic values of don't care bits such that soft errors are reduced. Our approaches are efficient and do not change LUT level placement and routing. Therefore, they are suitable for design closure. For the ten largest combinational MCNC benchmark circuits mapped for 6-LUTs, our approaches obtain 20% chip level Mean Time To Failure (MTTF) improvements, compared to the baseline mapped by Berkeley ABC mapper. They obtain 3× more chip level MTTF improvements and are 128× faster when compared to the existing best in-place IPD algorithm. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/FPL.2011.95 | FPL |
Keywords | Field | DocType |
lut level placement,dont care bits,network routing,in-place,lut routing,sram-based fpga,chip level mean time,design closure,sram chips,in-place x-filling,mitigate soft errors,chip level mttf improvement,soft error mitigation,chip level mean time to failure improvements,berkeley abc mapper,single event upsets,sram-based field programmable gate,lut configuration bit,large portion,best in-place ipd algorithm,field programmable gate arrays,logic values,don't care,soft error,sram-based fpgas,mitigation,field programmable gate array,mean time to failure,chip | Mean time between failures,Lookup table,Soft error,Computer science,Design closure,Field-programmable gate array,Real-time computing,Chip,Static random-access memory,Electronic circuit,Embedded system | Conference |
ISBN | Citations | PageRank |
978-0-7695-4529-5 | 5 | 0.63 |
References | Authors | |
10 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhe Feng | 1 | 51 | 5.25 |
| Naifeng Jing | 2 | 152 | 27.07 |
| Gengsheng Chen | 3 | 26 | 5.13 |
| Yu Hu | 4 | 75 | 9.62 |
| Lei He | 5 | 29 | 5.87 |