Name
Abstract | ||
|---|---|---|
We present a procedure to determine initialization sequences for a sequential circuit optimizing sequence length and unknown values (Xes) in the flip-flops. Specifically, we consider the following two problems: (1) Determine a sequence that initializes a maximal set of flip-flops starting in a completely unknown state. (2) Determine a minimal subset of flip-flops that need to be controllable such that the circuit can be completely initialized in a limited number of time frames. The underlying principle of our methods is a maximization formalism using formal optimization techniques based on satisfiability solvers (MaxSAT). We introduce several heuristics which increase the scalability of our approach significantly. Experimental results demonstrate the applicability of the method for large academic and industrial benchmark circuits with up to a few hundred thousand gates. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/VLSID.2014.18 | VLSI Design |
Keywords | Field | DocType |
industrial benchmark circuit,initialization sequence,sequential circuit,unknown state,unknown value,efficient sat-based circuit initialization,sequence length,larger designs,limited number,hundred thousand gate,formal optimization technique,maxsat,sequential circuits,sat,formal methods | Maximum satisfiability problem,Maximal set,Sequential logic,Computer science,Satisfiability,Algorithm,Heuristics,Initialization,Maximization,Scalability | Conference |
ISSN | Citations | PageRank |
1063-9667 | 1 | 0.36 |
References | Authors | |
13 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Matthias Sauer | 1 | 195 | 20.02 |
| sven reimer | 2 | 45 | 4.48 |
| Sudhakar M. Reddy | 3 | 5747 | 699.51 |
| Bernd Becker | 4 | 855 | 73.74 |