Name
Abstract | ||
|---|---|---|
Fast FPGA CAD tools that produce high quality results has been one of the most important research issues in the FPGA domain. Simulated annealing has been the method of choice for placement. However, simulated annealing is a very compute-intensive method. In our present work we investigate a range of parallelization strategies to speedup simulated annealing with application to placement for FPGA. We present experimental results obtained by applying the different parallelization strategies to the Versatile Place and Route (VPR) Tool, implemented on an SGI Origin shared memory multi-processor and an IBM-SP2 distributed memory multi-processor. The results show the tradeoff between execution time and quality of result for the different parallelization strategies. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1145/330855.330988 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
parallel algorithm,memory multi-processor,compute-intensive method,fpga domain,different parallelization strategy,fast fpga cad tool,present work,speedup simulated annealing,parallelization strategy,simulated annealing,fpga placement,high quality result,mems,verification,distributed memory,design,socs | Simulated annealing,Shared memory,Parallel algorithm,Computer science,Parallel computing,Field-programmable gate array,Place and route,Distributed memory,Real-time computing,Execution time,Speedup | Conference |
ISBN | Citations | PageRank |
1-58113-251-4 | 16 | 1.27 |
References | Authors | |
10 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Malay Haldar | 1 | 98 | 10.78 |
| Anshuman Nayak | 2 | 96 | 10.31 |
| Alok Choudhary | 3 | 322 | 31.06 |
| Prith Banerjee | 4 | 255 | 23.94 |