Name
Abstract | ||
|---|---|---|
The trend to multi-core chip designs presents new challenges for design automation, while the increased reuse of components may offer solutions. This paper describes some of the key challenges with attention paid to three enablers: a physical architecture to streamline chip integration, the linking of early analysis tools around shared data and an updated verification approach for multi-core designs. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1145/1278480.1278670 | Proceedings of the 50th Annual Design Automation Conference |
Keywords | Field | DocType |
multicore processing,floorplanning,integrated circuit design,thermal analysis,chip,system performance,application software,design,application specific integrated circuits,design automation,performance,verification | Analysis tools,Architecture,Reuse,Computer science,Real-time computing,Chip,Integrated circuit design,Electronic design automation,Multi-core processor,Floorplan | Conference |
ISSN | Citations | PageRank |
0738-100X | 6 | 0.57 |
References | Authors | |
10 | 1 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| John A. Darringer | 1 | 277 | 206.31 |