Paper Info
Title
An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems
Abstract
While the capacity of flash-memory storage systems keeps increasing significantly, effective and efficient management of flash-memory space has become a critical design issue! Different granularities in space management impose different management costs and mapping efficiency. In this paper, we explore an address translation mechanism that can dynamically and adaptively switch between two granularities in the mapping of logical block addresses into physical block addresses in flash memory management. The objective is to provide good performance in address mapping and space utilization and, at the same time, to have the memory space requirements, and the garbage collection overhead under proper management. The experimental results show that the proposed adaptive mechanism could provide significant performance improvement over the well-known coarse-grained management mechanism NFTL (NAND flash translation layer) over realistic workloads
Year
DOI
Venue
2006
10.1109/ICCAD.2006.320107
ICCAD
Keywords
Field
DocType
nand circuits,physical block address,efficient management,flash-memory space,flash memory management,nand flash translation layer,well-known coarsegrained management mechanism,storage management,memory space requirement,address mapping,flash-memory storage system,garbage collection,space utilization,address translation,flash memory,embedded systems,embedded system,different management cost,storage systems,flash translation layer,space management,adaptive two-level management,flash memories,proper management,storage system,operating system
Flash file system,Flash memory,Space management,Address mapping,Computer science,Real-time computing,NAND gate,Garbage collection,Critical design,Performance improvement
Conference
ISSN
ISBN
Citations 
1092-3152 E-ISBN : 1-59593-389-1
1-59593-389-1
97
PageRank 
References 
Authors
5.30
11
2
Name
Order
Citations
PageRank
Chin-Hsien Wu141947.93
Tei-Wei Kuo23203326.35