Abstract | ||
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This paper describes a quarter video graphic array/common intermediate format (QVGA/CIF) resolution MPEG-4 video codec based on a low-power, general-purpose digital signal processor (DSP) (NEC μPD77210, 160 MHz, 80 mW, 1.5 V). To enhance video codec performance, the codec employs fast algorithms, including, in motion estimation, a successive similarity detection algorithm (SSDA; a fast block matching) whose decision timing for termination of block matching is optimized. Further, the use of a software direct memory access (DMA) queue reduces the wasteful DSP wait cycles that can result from massive access to external frame memories. The resulting codec executes QVGA (320 × 240 pixels) × 15 fps codec, or CIF (352 × 288 pixels) × 15 fps encoding at 384 kbps, in real time, performance levels sufficient for next-generation wireless videotelephony. |
Year | DOI | Venue |
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2005 | 10.1023/B:VLSI.0000047268.39953.60 | Signal Processing Systems, 2002. |
Keywords | DocType | Volume |
MPEG-4,DSP,μPD77210,low power,computational cost,motion estimation,successive similarity detection algorithm (SSDA),DMA queue | Journal | 39 |
Issue | ISSN | Citations |
1-2 | 1520-6130 | 5 |
PageRank | References | Authors |
0.68 | 5 | 3 |
Name | Order | Citations | PageRank |
---|---|---|---|
Atsushi Hatabu | 1 | 33 | 3.79 |
Takashi Miyazaki | 2 | 5 | 0.68 |
Ichiro Kuroda | 3 | 148 | 23.39 |