Title
Estimation of Bus Performance for a Tuplespace in an Embedded Architecture
Abstract
This paper describes a design methodology for the estimation of bus performance of a tuplespace for factory automation. The need of a tuplespace is motivated by the characteristics of typical embedded architectures for factory automation. We describe the features of a bus for embedded applications and the problem of estimating its performance, and present a rapid prototyping design methodology developed for a qualitative and quantitative estimation. The methodology is based on a mix of different modeling languages such as Java, C++, SystemC and Network Simulator2 (NS2). Its application allows to estimate the expected performance of the bus under design in relation to the developed tuplespace.
Year
Venue
Keywords
2003
DATE
expected performance,developed tuplespace,quantitative estimation,factory automation,typical embedded architecture,rapid prototyping design methodology,bus performance,network simulator2,design methodology,embedded application,application software,embedded system,modeling language,automatic control,java,embedded systems,middleware
Field
DocType
ISBN
Rapid prototyping,Middleware,Computer science,Modeling language,Automation,SystemC,Real-time computing,Application software,Design space exploration,Java,Embedded system
Conference
0-7695-1870-2
Citations 
PageRank 
References 
3
0.67
4
Authors
5
Name
Order
Citations
PageRank
Nicola Drago1694.93
Franco Fummi21001111.62
Marco Monguzzi3121.32
Giovanni Perbellini411611.43
Massimo Poncino51309.16