Name
Abstract | ||
|---|---|---|
Long instruction word architectures, such as attached scientific processors and horizontally microcoded CPU's, are a popular means of obtaining code speedup via fine-grained parallelism. The falling cost of hardware holds out the hope of using these architectures for much more parallelism. But this hope has been diminished by experiments measuring how much parallelism is available in the code to start with. These experiments implied that even if we had infinite hardware, long instruction word architectures could not provide a speedup of more than a factor of 2 or 3 on real programs. |
Year | DOI | Venue |
|---|---|---|
1984 | 10.1109/TC.1984.1676371 | IEEE Trans. Computers |
Keywords | Field | DocType |
scientific processor,real program,long instruction word architectures,code speedup,fine-grained parallelism,long instruction word architecture,infinite hardware,parallelism available,popular mean,microcode,data processing,trace scheduling,programming language,very long instruction word | Instruction-level parallelism,Microcode,Computer architecture,Trace scheduling,Computer science,Very long instruction word,Task parallelism,Parallel computing,Data parallelism,Speedup | Journal |
Volume | Issue | ISSN |
33 | 11 | 0018-9340 |
Citations | PageRank | References |
89 | 38.97 | 12 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. Nicolau | 1 | 89 | 38.97 |
| joseph a fisher | 2 | 1410 | 264.50 |