Name
Abstract | ||
|---|---|---|
The regular 2-D mesh topology has been utilized for most of Network-on-Chips (NoCs) on FPGAs. Spatially biased traffic generated in some applications makes a customization method for removing links more efficient, since some links become low utilization. In this paper, a link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize the required hardware amount. Based on the pre-analyzed traffic information, links on which the communication amount is small are removed to reduce the hardware cost while maintaining adequate performance. Two policies are proposed to avoid deadlocks and they outperform up*/down* routing, which is a representative deadlock-free routing on irregular topology. In the case of the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1587/transinf.E92.D.575 | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS |
Keywords | Field | DocType |
network-on-chip, FPGA, customize, router | Mesh networking,System on a chip,Computer science,Deadlock,Field-programmable gate array,Network on a chip,Network architecture,Router,Integrated circuit,Embedded system | Journal |
Volume | Issue | ISSN |
E92D | 4 | 1745-1361 |
Citations | PageRank | References |
0 | 0.34 | 14 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daihan Wang | 1 | 82 | 4.78 |
| Hiroki Matsutani | 2 | 576 | 62.07 |
| Michihiro Koibuchi | 3 | 726 | 74.68 |
| Hideharu Amano | 4 | 1375 | 210.21 |