Name
Title | ||
|---|---|---|
Design and performance of a pixel-level pipelined-parallel architecture for high speed wavelet-based image compression |
Abstract | ||
|---|---|---|
Wavelets have widely been used in many signal and image processing applications. In this paper, a new serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet transform, which is realised using some FIFO memory modules implementing a pixel-level pipeline architecture to compress and decompress images. The real filter calculation over 4x4 window blocks is done using a tree of carry save adders to ensure the high speed processing required for many applications. The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis reveals that the proposed architecture, implemented using current VLSI technologies, can process a video stream in real time. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1016/j.compeleceng.2005.07.005 | Computers & Electrical Engineering |
Keywords | Field | DocType |
image processing application,pixel-level pipeline architecture,4-tap wavelet,high speed processing,decompress image,new serial-parallel architecture,wavelet-based image compression,pixel-level pipelined-parallel architecture,real filter calculation,real time,proposed architecture,compression,wavelet transform,pipelining,performance,image compression,signal and image processing,image processing,carry save adder | Pipeline (computing),FIFO (computing and electronics),Computer science,Image processing,Real-time computing,Digital image processing,Computer hardware,Very-large-scale integration,Image compression,Wavelet transform,Wavelet | Journal |
Volume | Issue | ISSN |
31 | 8 | Computers and Electrical Engineering |
Citations | PageRank | References |
5 | 0.67 | 10 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. Masoudnia | 1 | 5 | 0.67 |
| H. Sarbazi-Azad | 2 | 375 | 32.94 |
| S. Boussakta | 3 | 135 | 11.59 |