Title
The design of a low-power high-speed current comparator in 0.35-µm CMOS technology
Abstract
A novel low power with high performance low current comparator is proposed in this paper which comprises of low input impedance using a simple biasing method. It aimed for low power consumption and high speed designs compared with other high speed designs. The simulation results from HSPICE demonstrate the propagation delay is about 0.7 ns and the average power consumption is 130 muW for 100 nA input current at supply voltage of 1.8 V using 0.35 micron CMOS technology.
Year
DOI
Venue
2009
10.1109/ISQED.2009.4810278
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Keywords
DocType
ISBN
average power consumption,low input impedance,novel low power,low-power high-speed current comparator,high speed design,nA input,high performance,low power consumption,low current comparator,m CMOS technology,high speed,micron CMOS technology
Conference
978-1-4244-2953-0
Citations 
PageRank 
References 
0
0.34
0
Authors
6
Name
Order
Citations
PageRank
Soheil Ziabakhsh153.68
Hosein Alavi-Rad2413.52
Mohammad Alavi-Rad300.34
Mohammad Mortazavi4366.28
Alavi-Rad, H.500.34
Alavi-Rad, M.600.34