Name
Abstract | ||
|---|---|---|
High-end hardware design flows mandate a variety of sequential transformations to address needs such as performance, power, post-silicon debug and test. Industrial demand for robust sequential equivalence checking (SEC) solutions is thus becoming increasingly prevalent. In this paper, we discuss the role of SEC within IBM. We motivate the need for a highly-automated scalable solution, which is robust against a variety of design transformations - including those that alter initialization sequences. This motivation has caused us to embrace the paradigm of SEC with respect to designated initial states. We furthermore describe the diverse set of algorithms comprised within our SEC framework, which we have found necessary for the automated solution of the most complex SEC prob- lems. Finally, we provide several experiments illustratin g the necessity of our diverse algorithm flow to efficiently solve difficult SEC problems involving a variety of design transformations. |
Year | Venue | Keywords |
|---|---|---|
2006 | ICCD | robustness,hardware,design optimization,equivalence checking,sequential analysis,scalability,logic design |
Field | DocType | Citations |
Logic synthesis,Formal equivalence checking,Computer science,Real-time computing,Theoretical computer science,Robustness (computer science),Design flow,Register-transfer level,Initialization,Scalability,Debugging | Conference | 33 |
PageRank | References | Authors |
1.37 | 27 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jason Baumgartner | 1 | 313 | 23.36 |
| Hari Mony | 2 | 186 | 13.30 |
| Viresh Paruthi | 3 | 371 | 21.84 |
| Robert Kanzelman | 4 | 107 | 6.16 |
| Geert Janssen | 5 | 127 | 8.90 |