Title
FPGA Implementation of a Synchronous and Self-Timed Neuroprocessor
Abstract
This article presents the implementation of a neuroprocessor based on a self-organizing map (SOM) architecture. The processor presents a hybrid structure both synchronous and self-timed. Where the neuronal network blocks (SOM) are synchronized with a protocol of 4 phases, for the control of data flow. The neuroprocessor was designed for the analysis and classification of tension deformation patterns of the knee ligaments. The circuit is programmable and recognizes different sequences of movement patterns for a knee joint with damage to the anterior cruciate ligament (ACL). This design is part of an electronic system for the rehabilitation of injuries to the ACL and the dynamic study of the knee. The circuit is implemented in an FPGA Virtex II.
Year
DOI
Venue
2005
10.1109/RECONFIG.2005.17
ReConFig
Keywords
Field
DocType
field programmable gate arrays,neuronal network,data flow
Computer science,Field-programmable gate array,Electronic systems,Virtex,Anterior cruciate ligament,Knee Joint,Data flow diagram,Embedded system
Conference
ISBN
Citations 
PageRank 
0-7695-2456-7
2
0.42
References 
Authors
3
3
Name
Order
Citations
PageRank
Juan José Raygoza-Panduro150.91
Susana Ortega-Cisneros2256.85
Eduardo Boemo3122.11