Name
Title | ||
|---|---|---|
Synthesis of Synchronous Sequential Logic Circuits from Partial Input/Output Sequences |
Abstract | ||
|---|---|---|
This work takes a different approach to synthesize a synchronous sequential logic circuit. The input of the synthesizer is
a partial input/output sequence. This type of specification is not suitable for conventional synthesis methods. Genetic Algorithm
(GA) was applied to synthesize the desired circuit that performs according to the input/output sequences. GA searches for
circuits that represent the desired state transition function. Additional combination circuits that map states to the corresponding
outputs are synthesized by conventional methods. The target of our synthesis is a type of registered Programmable Array Logic
which is commercially available as GAL. We are able to synthesize various types of synchronous sequential logic circuit such
as counter, serial adder, frequency divider, modulo-5 detector and parity checker.
|
Year | DOI | Venue |
|---|---|---|
1998 | 10.1007/BFb0057611 | ICES |
Keywords | Field | DocType |
output sequences,partial input,synchronous sequential logic circuits,combinational circuit,input output,state transition,genetic algorithm | Sequential logic,Pass transistor logic,Computer science,Programmable Array Logic,Logic optimization,Algorithm,Input/output,Synchronous circuit,Register-transfer level,Asynchronous circuit | Conference |
Volume | ISSN | ISBN |
1478 | 0302-9743 | 3-540-64954-9 |
Citations | PageRank | References |
9 | 0.69 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chaiyasit Manovit | 1 | 114 | 6.48 |
| Chatchawit Aporntewan | 2 | 34 | 4.14 |
| Prabhas Chongstitvatana | 3 | 132 | 22.34 |