Name
Abstract | ||
|---|---|---|
Nowadays, hardware devices are meant to host the execution of many complex, multicore applications, whose functional and nonfunctional requirements vary according to the specific working domain. In this work, we propose a design methodology that combines an efficient reconfigurable architecture and a related mapping flow. In particular, the proposed island-based hardware architecture couples an efficient area usage and an adaptable communication infrastructure. The proposed mapping flow distributes the cores on the device to optimize both performance and reconfiguration related metrics. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/LES.2011.2115991 | Embedded Systems Letters |
Keywords | Field | DocType |
island-based adaptable,adaptable communication infrastructure,hardware device,efficient reconfigurable architecture,efficient area usage,system design,multicore application,design methodology,proposed mapping flow,related mapping flow,reconfiguration related metrics,proposed island-based hardware architecture,hardware,field programmable gate arrays,integrated circuit design,transform coding,embedded systems,decoding,computer architecture,system on chip,reconfigurable computing,field programmable gate array,switches,system on a chip | System on a chip,Computer science,Parallel computing,Field-programmable gate array,Platform-based design,Multi-core processor,Non-functional requirement,Control reconfiguration,Embedded system,Hardware architecture,Reconfigurable computing | Journal |
Volume | Issue | ISSN |
3 | 2 | 1943-0663 |
Citations | PageRank | References |
3 | 0.54 | 11 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| I. Beretta | 1 | 3 | 0.54 |
| V. Rana | 2 | 3 | 0.54 |
| D. Atienza | 3 | 182 | 24.26 |
| D. Sciuto | 4 | 1720 | 176.61 |