Name
Abstract | ||
|---|---|---|
We propose a series of aggressive register deallocation mechanisms to reduce the register file pressure and increase the parallelism exploited by superscalar microprocessors. Our techniques are based on a key observation that a register value can be temporarily decoupled from the register identifier. Specifically, even if a physical register is deallocated, the value is still available in the register and can be read by the dependent instructions until the register is overwritten. In these situations, we can effectively overlap the consumption of the produced register value and partial processing of the instruction that gets the same register reassigned to it. In this paper, we propose several realizations of the address-value decoupling idea and discuss their implications on the performance. Our most aggressive scheme achieves an average IPC speedup of 14.6% across simulated SPEC 2000 benchmarks. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ICPP.2006.20 | ICPP |
Keywords | Field | DocType |
register value,aggressive scheme,address-value decoupling,early register deallocation,address-value decoupling idea,dependent instruction,register identifier,aggressive register deallocation mechanism,register file pressure,average ipc speedup,physical register,key observation,register file | Status register,Register allocation,Memory data register,Computer science,Parallel computing,Stack register,Control register,Register window,Memory address register,Memory buffer register | Conference |
ISSN | ISBN | Citations |
0190-3918 | 0-7695-2636-5 | 7 |
PageRank | References | Authors |
0.48 | 27 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Deniz Balkan | 1 | 145 | 6.80 |
| Joseph Sharkey | 2 | 30 | 2.37 |
| Dmitry Ponomarev | 3 | 893 | 56.45 |
| Aneesh Aggarwal | 4 | 202 | 16.91 |