Paper Info
Title
Analysis Of Control-Delay Reduction For The Improvement Of Ups Voltage-Loop Bandwidth
Abstract
This paper investigates the effects of control-delay minimization in the dynamic performance of the output stage of uninterruptible power supplies (UPSs) by shifting the sampling time of inductor current and output voltage toward the duty-cycle update instant. This paper shows how a small shift of the output-voltage sampling can significantly increase the UPS voltage-loop bandwidth while keeping the same stability margin. Instead, less contribution comes from the delay minimization of the inductor-current sampling, so that current-ripple cancellation techniques are not needed. A detailed model based on the modified Z-transform, which accounts for different time delays in multiloop control, is proposed. The effectiveness of the proposed analysis is demonstrated by simulation and experimental results on a typical industrial three-phase/three-phase 8-kHz 30-kVA UPS prototype. By using two control designs based on the same phase margin, the output-voltage total harmonic distortion with the normalized distorting load is reduced from 6.8% to 5.7%, using a delay of the output voltage sampling equal to 25 mu s.
Year
DOI
Venue
2008
10.1109/TIE.2008.918607
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
Keywords
Field
DocType
delay effects, digital control, digital-signal processors, uninterruptible power supply (UPS), voltage control
Total harmonic distortion,Digital signal processor,Control theory,Voltage,Inductor,Electronic engineering,Control engineering,Bandwidth (signal processing),Phase margin,Sampling (statistics),Engineering,Digital control
Journal
Volume
Issue
ISSN
55
8
0278-0046
Citations 
PageRank 
References 
7
1.27
6
Authors
4
Name
Order
Citations
PageRank
Paolo Mattavelli121035.11
Filippo Polo271.27
Flavio Dal Lago371.27
Stefano Saggini4143.08