Name
Abstract | ||
|---|---|---|
This paper describes an integrated ISFETs instrumentation system in a 0.18 μm 1-poly-6-metal CMOS process. The chip is able to compute the average of CMOS ISFETs' threshold voltages by using an averaging array employing global negative current feedback. In addition, neither reference voltage nor current is required to set up the sigma-delta modulator because the internal signal is converted and processed in the frequency domain. The chip operates at 3.3 V for the analog blocks and the digital input/output blocks, and at 1.8 V for the core digital logic. It achieves 8 bits accuracy under 80 μW static power consumption. The die area is 2.6 mm2. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/JSSC.2010.2053863 | J. Solid-State Circuits |
Keywords | Field | DocType |
cmos integrated circuits,sigma-delta modulator,current feedback opamp,sigma-delta modulation,averaging array,power consumption,integrated isfet instrumentation system,log domain,power 80 muw,isfets array,internal signal,cmos isfet,voltage 3.3 v,die area,isfet,voltage 1.8 v,current feedback,frequency modulator,size 0.18 mum,vco,negative current feedback,threshold voltage,averaging,ion sensitive field effect transistors,chip organization,analog blocks,digital input/output blocks,static power consumption,digital logic,l-poly-6-metal cmos process,logic gates,chip,sigma delta modulator,electric potential,frequency modulation,frequency domain,input output | Logic gate,Computer science,Voltage reference,8-bit,Voltage-controlled oscillator,Electronic engineering,CMOS,Chip,Delta-sigma modulation,Electrical engineering,Operational amplifier | Journal |
Volume | Issue | ISSN |
45 | 9 | 0018-9200 |
Citations | PageRank | References |
5 | 1.23 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wai Pan Chan | 1 | 5 | 1.57 |
| Bhusana Premanode | 2 | 21 | 3.45 |
| Christofer Toumazou | 3 | 265 | 59.06 |