Name
Abstract | ||
|---|---|---|
Loop tiling is a fundamental optimization for improving data locality. Selecting the right tile size combined with the parallelization of loops can provide additional performance increases in the modern of Chip MultiProcessor (CMP) architectures. This paper presents a runtime optimization system which automatically parallelizes loops and searches empirically for the best tile sizes on a scalable multi-cluster CMP. The system is built on top of a virtual machine and targets the runtime parallelization and optimization of Java programs. Experimental results show that runtime parallelization and tile size searching are capable of improving performance for two BLAS kernels and one Lattice-Boltzmann simulation, despite overheads. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1007/978-3-540-69501-1_23 | ICA3PP |
Keywords | Field | DocType |
adaptive loop tiling,additional performance increase,runtime optimization system,runtime parallelization,multi-cluster cmp,fundamental optimization,chip multiprocessor,blas kernel,right tile size,best tile size,tile size,java program,lattice boltzmann,automatic parallelization,loop tiling,virtual machine | Locality,Virtual machine,Computer science,Parallel computing,Chip,Loop tiling,Multiprocessing,Java,Automatic parallelization,Scalability | Conference |
Volume | ISSN | Citations |
5022 | 0302-9743 | 4 |
PageRank | References | Authors |
0.43 | 14 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jisheng Zhao | 1 | 480 | 24.34 |
| Matthew Horsnell | 2 | 14 | 2.33 |
| Mikel Luján | 3 | 540 | 46.40 |
| Ian Rogers | 4 | 8 | 0.87 |
| Chris Kirkham | 5 | 267 | 13.74 |
| Ian Watson | 6 | 49 | 4.65 |