Name
Title | ||
|---|---|---|
Improving latency tolerance of network processors through simultaneous multithreading |
Abstract | ||
|---|---|---|
Existing multithreaded network processors architecture with multiple processing engines (PEs), aims at taking advantage of blocked multithreading technique which executes instructions of different user-defined threads in the same PE pipeline, in explicit and interleave way. Multiple PEs, each of which is a multithreaded processor core, process several packets in parallel to hide long memory access latency. Most of them are optimized for throughputs mostly in data-plane. In future network workloads, the boundaries between data-plane and control-plane become blurred, so that PEs are demanded not only wire speed packet forwarding on data-plane, but also highly intelligent and increased complex packet processing function on control-plane. In this paper, we analyze SMT’s short latency tolerance potential when used in out-of-order and dynamic scheduling PE cores. We show in this paper that 2~4 issue SMT provides an excellent short memory and branch latency tolerance, which gain higher instructions throughout as well as much simpler structures. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1007/11573937_9 | APPT |
Keywords | Field | DocType |
multiple pes,improving latency tolerance,branch latency tolerance,issue smt,dynamic scheduling pe core,future network workloads,excellent short memory,long memory access latency,simultaneous multithreading,complex packet processing function,short latency tolerance potential,pe pipeline,network processor,process engineering,packet forwarding,long memory,out of order,dynamic scheduling | Network processor,Multithreading,Latency (engineering),Computer science,Parallel computing,Distributed memory,Simultaneous multithreading,Packet processing,Multi-core processor,Packet forwarding,Embedded system | Conference |
Volume | ISSN | ISBN |
3756 | 0302-9743 | 3-540-29639-5 |
Citations | PageRank | References |
0 | 0.34 | 9 |
Authors | ||
4 | ||