Name
Abstract | ||
|---|---|---|
Despite generation upon generation of scaling, computer chips have until now remained essentially 2-dimensional. Improvements in on-chip wire delay and in the maximum number of I/O per chip have not been able to keep up with transistor performance growth; it has become steadily harder to hide the discrepancy. 3D chip technologies come in a number of flavors, but are expected to enable the extension of CMOS performance. Designing in three dimensions, however, forces the industry to look at formerly-two-dimensional integration issues quite differently, and requires the re-fitting of multiple existing EDA capabilities. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1145/1278480.1278623 | Proceedings of the 50th Annual Design Automation Conference |
Keywords | Field | DocType |
chip,performance,assembly,3d chip,copper,microelectronics,cmos integrated circuits,3d,cmos technology,integrated circuit design,packaging,2 dimensional,bandwidth,theory,three dimensions,design,standardization,latency,interconnect | Computer science,CMOS,Chip,Electronic engineering,Integrated circuit design,Bandwidth (signal processing),Three-dimensional integrated circuit,Interconnection,Transistor,Electrical engineering,Wafer-scale integration | Conference |
ISSN | Citations | PageRank |
0738-100X | 56 | 4.04 |
References | Authors | |
12 | 11 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kerry Bernstein | 1 | 85 | 7.41 |
| Paul Andry | 2 | 56 | 4.04 |
| Jerome Cann | 3 | 56 | 4.04 |
| Philip G. Emma | 4 | 225 | 28.55 |
| David Greenberg | 5 | 56 | 4.04 |
| Wilfried Haensch | 6 | 389 | 36.68 |
| Mike Ignatowski | 7 | 192 | 11.60 |
| Steve Koester | 8 | 56 | 4.04 |
| John Magerlein | 9 | 81 | 7.51 |
| Ruchir Puri | 10 | 515 | 71.90 |
| Albert Young | 11 | 58 | 4.51 |