Title
Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration
Abstract
High parallelism degree is fundamental for high speed image processing systems. Modern FPGA devices can provide such parallelism plus flexibility. Temporal partitioning techniques can be used to implement large systems, splitting them into partitions (called contexts), multiplexed in a FPGA. This approach can increase the effective FPGA area, allowing high parallelism in the application tasks. However, the context reconfigurations can cause performance decrease. Intensive parallelism exploration of massive image data application compensates this overhead and can improve global performance. In this work, one reconfigurable computer platform and design space exploration techniques are proposed for mapping of image processing applications into FPGA slices. A library with different hardware implementation for different parallelism degree is used to better adjust space/time for each task. Experiments demonstrate the efficiency of the approach when compared to the optimal mapping reached by exhaustive timing search in the complete design space exploration.
Year
DOI
Venue
2006
10.1145/1150343.1150361
SBCCI
Keywords
Field
DocType
effective fpga area,high parallelism,temporal partitioning,modern fpga device,high speed image processing,complete design space exploration,design space exploration technique,fpga slice,image processing system,high parallelism degree,different parallelism degree,fpga computer,intensive parallelism exploration,space time,image processing,reconfigurable computing
Instruction-level parallelism,Computer architecture,Computer science,Task parallelism,Image processing,Field-programmable gate array,Real-time computing,Data parallelism,Multiplexing,Design space exploration
Conference
ISBN
Citations 
PageRank 
1-59593-479-0
2
0.41
References 
Authors
13
4