Title
A case study on applying bounded model checking to analog circuit verification.
Year
Venue
Field
2006
MBMV
Model checking,Computer science,Algorithm,Theoretical computer science,Symbolic trajectory evaluation,Bounded function
DocType
Citations 
PageRank 
Conference
0
0.34
References 
Authors
0
4
Name
Order
Citations
PageRank
Alexander Jesser1152.15
Markus Wedler27712.44
Lars Hedrich326731.08
Wolfgang Kunz423633.71