Name
Abstract | ||
|---|---|---|
Using multiple levels of cache memory is becoming increasingly popular to bridge the gap between CPU and memory cycle times, but the design of a multi-level cache hierarchy is challenging. One complication is maintaining the inclusion property, where each cache contains a superset of the data contained in all the smaller caches whose requests it services. Inclusion is important for minimizing the coherence overhead; if it is maintained, first level caches will receive coherence signals only for those blocks or lines that they actually contain. The authors show that the straightforward method of maintaining inclusion can lead to unrealistic set associativity requirements in the second level caches. The authors describe weak inclusion, an alternate method of ensuring inclusion with reduced set associativity requirements. |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1109/SPDP.1991.218256 | Dallas, TX |
Keywords | Field | DocType |
degradation,cycle time,protocols,cache memory | Tag RAM,Subset and superset,Associative property,CPU cache,Cache,Computer science,Parallel computing,Multiprocessing,Bus sniffing,Distributed computing,Cache coherence | Conference |
ISBN | Citations | PageRank |
0-8186-2310-1 | 1 | 0.36 |
References | Authors | |
5 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Brent E. Nelson | 1 | 616 | 79.91 |
| James K. Archibald | 2 | 632 | 161.01 |
| J. Kelly Flanagan | 3 | 1 | 0.36 |