Name
Abstract | ||
|---|---|---|
A leakage-efficient cache controller design targeted on ultra low power embedded processors is proposed. The key insight is that a large circuits subset is accessed only when cache misses happen. By utilizing the fine-grained run-time power gating technique, such a subset can be dynamically powered-off as a power gated domain. Two simple but effective sleeping control policies are proposed to assure the leakage reduction effect; and to eliminate the impact of wake-up process, a latency cancellation mechanism is also proposed. Evaluation results show, in 90nm CMOS technology, 69% and 64% of leakage power can be reduced for instruction cache controller and data cache controller without performance degradation. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1007/978-3-642-00454-4_18 | ARCS |
Keywords | Field | DocType |
embedded processor | Pipeline burst cache,Cache pollution,Computer science,Cache,Parallel computing,Real-time computing,Cache algorithms,Page cache,Cache coloring,Bus sniffing,Smart Cache,Embedded system | Conference |
Volume | ISSN | Citations |
5455 | 0302-9743 | 0 |
PageRank | References | Authors |
0.34 | 7 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lei Zhao | 1 | 22 | 3.05 |
| Hui Xu | 2 | 1 | 1.03 |
| Naomi Seki | 3 | 40 | 3.30 |
| Yoshiki Saito | 4 | 35 | 4.52 |
| Yohei Hasegawa | 5 | 103 | 12.78 |
| Kimiyoshi Usami | 6 | 528 | 75.61 |
| Hideharu Amano | 7 | 1375 | 210.21 |