Name
Abstract | ||
|---|---|---|
For large circuits, static timing analysis (STA) needs to be performed in a hierarchical manner to achieve higher performance in arrival time propagation. In hierarchical STA, efficient and accurate timing models of sub-modules need to be created. We propose a timing model extraction method that significantly reduces the size of timing models without losing any accuracy by removing redundant timing information. Circuit components which do not contribute to the delay of any input to output pair are removed. The proposed method is deterministic. Compared to the original models, the numbers of edges and vertices of the resulting timing models are reduced by 84% and 85% on average, respectively, which are significantly more than the results achieved by other methods. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1007/978-3-540-95948-9_16 | Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation |
Keywords | Field | DocType |
resulting timing model,accurate timing model,static timing,timing model,combinational circuits,timing model extraction method,arrival time propagation,model extraction,hierarchical manner,redundant timing information,hierarchical sta,static timing analysis,combinational circuit | Vertex (geometry),Computer science,Parallel computing,Electronic engineering,Combinational logic,Real-time computing,Static timing analysis,Model extraction,Electronic circuit | Conference |
Volume | ISSN | Citations |
abs/1705.02610 | 0302-9743 | 0 |
PageRank | References | Authors |
0.34 | 6 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bing Li | 1 | 172 | 33.77 |
| Christoph Knoth | 2 | 11 | 2.08 |
| Walter Schneider | 3 | 0 | 0.34 |
| Manuel Schmidt | 4 | 41 | 3.71 |
| Ulf Schlichtmann | 5 | 645 | 70.67 |