Paper Info
Title
A half rate CDR with DCD cleaning up and quadrature clock calibration for 20Gbps 60GHz communication in 65nm CMOS
Abstract
A half-rate clock and data recovery (CDR) circuit for 60GHz communication with 20Gbps QPSK modulation in 65nm CMOS is presented. A hybrid DC-offset cancellation loop (DCOC) is proposed to calibrate the input offset. A duty cycle distortion (DCD) cleaning up circuit is adopted to minimize the negative impact on the half rate sampling in the CML-CMOS conversion, and a quadrature clock calibration (QCC) is utilized to correct the input clock I/Q phase mismatch. The CDR is based on phase interpolator (PI) and uses the quadrature clocks from the divider of the main PLL. The whole CDR consumes less than 16mW with 1V power supply and achieves less than 1mV DC-offset, 0.2% DCD and less than 1° residual I/Q phase mismatch after calibration.
Year
DOI
Venue
2013
10.1109/ISCAS.2013.6572008
ISCAS
Keywords
Field
DocType
cmos integrated circuits,size 65 nm,input offset,dcd cleaning,phase locked loop,half rate clock and data recovery circuit,hybrid dc-offset cancellation loop,pll,phase mismatch,quadrature phase shift keying,phase locked loops,qpsk modulation,cmos integrated circuit,frequency 60 ghz,duty cycle distortion cleaning,bit rate 20 gbit/s,quadrature clock calibration,phase interpolator,field effect mimic,half rate cdr,clock and data recovery circuits,radiocommunication,calibration,synchronization,phase shift keying,digital filters
Phase-locked loop,Synchronization,Digital filter,Computer science,Control theory,Half Rate,CMOS,Electronic engineering,Quadrature (mathematics),Offset (computer science),Phase-shift keying
Conference
Volume
Issue
ISSN
null
null
0271-4302
ISBN
Citations 
PageRank 
978-1-4673-5760-9
0
0.34
References 
Authors
2
6
Name
Order
Citations
PageRank
Xiaobao Yu1314.82
Baoyong Chi218451.00
Wei Meng329430.14
Wang A.Z.41612.73
Tianling Ren52511.75
Zhihua Wang6775190.44