Title
Digital oscillation-test method for delay and stuck-at fault testing of digital circuits
Abstract
Testing delay faults is becoming critical in new deepsubmicron digital circuits. This paper introduces a newtechnique for delay and stuck-at fault testing in digitalintegrated circuits. The proposed technique consists ofsensitizing a path in the digital circuit under test andthen incorporating it in a ring oscillator to test for delayand stuck-at faults in the path. This procedure should beexercised for all or at least critical paths in the circuit.To establish oscillations, we should make sure that thereis an odd number of inverters in the loop. This techniquecan be used along with scan techniques or be implementedas a built-in self-test technique. Benchmark resultsconfirm the efficiency of the proposed technique.The technique has been implemented in practice for an 8-bit digital adder on a field programmable device.
Year
DOI
Venue
1998
10.1109/TEST.1998.743141
ITC
Keywords
Field
DocType
stuck-at fault testing,8-bit digital adder,delayand stuck-at fault,built-in self-test technique,digital circuit,digital oscillation-test method,proposed technique,digitalintegrated circuit,critical path,testing delay fault,new deepsubmicron digital circuit,test methods,oscillations,digital circuits,adders,ring oscillator
Stuck-at fault,Digital integrated circuits,Test method,Oscillation,Digital electronics,Ring oscillator,Adder,Computer science,Electronic engineering,Digital delay line,Real-time computing
Conference
ISSN
ISBN
Citations 
1089-3539
0-7803-5093-6
15
PageRank 
References 
Authors
1.07
7
4
Name
Order
Citations
PageRank
Karim Arabi133839.18
Hassan Ihs2202.35
Christian Dufaza3485.87
Bozena Kaminska41155189.76