Paper Info
Title
Optimizing Throughput and Latency under Given Power Budget for Network Packet Processing
Abstract
Current state-of-the-art task scheduling algorithms for network packet processing schedule the program into a parallel-pipeline topology on network processors to maximize the throughput. However, there has been no existing work targeting power budget for packet processing on off-the-shelf multicore architectures. As energy consumption, reliability and cooling cost for packet processing systems become increasingly important, it is necessary to integrate power-awareness into a scheduler to meet the power budget. In this paper, we propose a novel scheduling algorithm to optimize both throughput and latency given a power budget for network packet processing on multicore architectures. This algorithm addresses power-aware parallel-pipeline scheduling problem by applying per-core DVFS to optimally adjust frequency on each core. We implement our algorithm on an AMD machine with two Quad-Core Opteron 2350 processors and compare the results with existing algorithms given the same power budget. For six real packet processing applications, our algorithm improves throughput and reduces latency by an average of 64.6% and 25.2%, respectively.
Year
DOI
Venue
2010
10.1109/INFCOM.2010.5462123
INFOCOM
Keywords
Field
DocType
task scheduling algorithms,processor scheduling,power aware computing,microprocessor chips,amd machine,quad core opteron 2350 processor,data communication equipment,latency,multicore architecture,algorithm address,per core dvfs,network packet processing schedule,network processor,novel scheduling algorithm,computer networks,current state-of-the-art task scheduling,power aware parallel pipeline scheduling,optimizing throughput,packet processing system,real packet processing application,network packet processing,throughput optimization,packet processing,power budget,pipeline processing,throughput,scheduling problem,scheduling algorithm,pipelines,process scheduling,multicore processing,network topology,mathematical model,silicon
Power budget,Network processor,Computer science,Scheduling (computing),Network packet,Network scheduler,Computer network,Packet processing,Throughput,Processing delay,Embedded system
Conference
ISSN
ISBN
Citations 
0743-166X
978-1-4244-5836-3
9
PageRank 
References 
Authors
0.58
16
2
Name
Order
Citations
PageRank
Jilong Kuang13817.00
Laxmi N. Bhuyan22393248.44