Name
Abstract | ||
|---|---|---|
The architectures of general purpose digital signal processors fail to deliver acceptable performance for multichannel signal processing. This paper describes a 40K transistor execution unit that is optimised for the processing of multichannel signals. The signal processor incorporates two 12 bit array multipliers and a 128 deep programmable delay line. To facilitate the programming of the device, it is designed to function as a memory mapped peripheral to a 16/32 bit microprocessor. It supports online diagnostics through the incorporation of shadow accumulators. It is fabricated in SCL's 2/spl mu/m double metal CMOS process and packaged in a 144 pin CPGA. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/ICVD.1995.512095 | VLSI Design |
Keywords | Field | DocType |
bit array multiplier,general purpose,m double metal cmos,signal processor,multichannel signal processing,single chip,deep programmable delay line,bit microprocessor,multichannel signal,digital signal processor,acceptable performance,chip,adders,filter bank,finite impulse response filter,signal processing,vlsi,transfer functions,digital signal processors | 32-bit,Signal processing,Digital signal processor,Computer science,Microprocessor,Filter bank,Electronic engineering,Chip,Execution unit,Computer hardware,Very-large-scale integration | Conference |
ISSN | ISBN | Citations |
1063-9667 | 0-8186-6905-5 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Krishnakumar, S. | 1 | 0 | 0.34 |
| Suresh, P. | 2 | 4 | 1.95 |
| Sadashiva Rao, S. | 3 | 0 | 0.34 |
| M. P. Pareek | 4 | 0 | 0.34 |
| rajiv gupta | 5 | 4301 | 364.53 |