Name
Abstract | ||
|---|---|---|
A sequentiality study for mixed-signal VLSI implementations of neuro/fuzzy feedforward algorithms is presented. Implications of sequential processing and mixed-signal operation are derived. Basic building blocks for sequential mixed-signal neural and fuzzy computing are proposed, and two example sequential processors are described. Feedback from designed processors and subcircuits allows consideration of the technology constraints for analysis and extension to different sequentiality degrees |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/ISCAS.2000.857448 | Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium |
Keywords | Field | DocType |
CMOS integrated circuits,VLSI,feedforward neural nets,fuzzy logic,mixed analogue-digital integrated circuits,neural chips,fuzzy feedforward algorithms,fuzzy sequential processors,mixed-signal VLSI implementations,mixed-signal operation,neural feedforward algorithms,neural sequential processors,sequential processing,sequentiality analysis,technology constraints | Fuzzy electronics,Neuro-fuzzy,Computer science,Fuzzy logic,CMOS,Electronic engineering,Time delay neural network,Adaptive neuro fuzzy inference system,Very-large-scale integration,Feed forward | Conference |
Volume | ISBN | Citations |
5 | 0-7803-5482-6 | 2 |
PageRank | References | Authors |
0.54 | 8 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Madrenas, J. | 1 | 2 | 0.54 |
| E. Alarcón | 2 | 3 | 0.93 |
| Cosp, J. | 3 | 20 | 2.70 |
| J. M. Moreno | 4 | 6 | 1.45 |
| A. Poveda | 5 | 8 | 3.24 |
| J. Cabestany | 6 | 34 | 5.44 |