Abstract | ||
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DVS is becoming an essential feature of state-of-the-art mobile processors. Interval-based DVS algorithms are widely employed in general purpose operating systems thanks to their simplicity and transparency. Such algorithms have a few problems, however, such as delayed response, prediction inaccuracies, and underestimation of the performance demand. In this paper we propose TSB (time slice based), a new DVS algorithm that takes advantage of the high transition speeds available in state-of-the-art processors. TSB adjusts processor performance at every context switch in order to match the performance demand of the next scheduled task. The performance demand of a task is predicted by analyzing its usage pattern in the previous time slice. TSB was evaluated and compared to other interval-based power management algorithms on the Linux kernel. The results show that TSB achieved similar or better energy efficiency compared to existing interval-based algorithms. In addition, TSB dramatically reduced the side effect of prolonging short-term execution times. For a task requiring 50ms to run without a DVS algorithm, TSB prolonged the execution time by only 6% compared to results of 136% for CPUSpeed and 20% for Ondemand. |
Year | DOI | Venue |
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2008 | 10.1016/j.sysarc.2007.03.006 | Journal of Systems Architecture - Embedded Systems Design |
Keywords | DocType | Volume |
short-term execution time,execution time,general purpose operating system,dvs algorithm,dynamic voltage scaling,next scheduled task,processor performance,new dvs algorithm,quick response,89.20.ff,performance demand,interval-based algorithm,interval-based dvs algorithm,low-power techniques,previous time slice,operating system | Journal | 54 |
Issue | ISSN | Citations |
1-2 | Journal of Systems Architecture | 7 |
PageRank | References | Authors |
0.50 | 10 | 4 |
Name | Order | Citations | PageRank |
---|---|---|---|
Euiseong Seo | 1 | 354 | 24.20 |
Seon-Yeong Park | 2 | 544 | 27.66 |
Jinsoo Kim | 3 | 78 | 28.26 |
Joonwon Lee | 4 | 1438 | 90.35 |