Abstract | ||
---|---|---|
Modern networks-on-chip (NoC) systems are required to handle complex run-time traffic patterns and unprecedented applications. Data traffics of these applications are difficult to be fully comprehended at design-time so as to optimize the network design. However, it has been discovered that the majority data flows in a network are dominated by less than 10% of the specific pathways. In this paper, we introduce a method that is capable of identifying critical pathways in a network at run-time and, then, can dynamically reconfigure the network to optimize for the network performance subjected to the identified dominated flows. An online learning and analysis scheme is employed to quickly discover the emerged dominated traffic flows and provides a statistical traffic prediction using regression analysis. The architecture of a self-tuning network is also discussed which can be reconfigured by setting up the identified point-to-point paths for the dominance data flows in large traffic volumes. The merits of this new approach are experimentally demonstrated using comprehensive NoC simulators. Compared to the conventional network architectures over a range of realistic applications, the proposed self-tuning network approach can effectively reduce the latency and power consumption by as much as 25% and 24%, respectively. We also evaluated the configuration time and additional hardware cost. This new approach demonstrates the capability of an adaptive NoC to handle more complex and dynamic applications. |
Year | DOI | Venue |
---|---|---|
2014 | 10.1145/2544375.2544393 | ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers |
Keywords | DocType | Volume |
point-to-point paths,self-tuning network approach,self-tuning networks-on-chip,complex runtime traffic pattern,dynamic network-flow dominance adaptation,majority data flows,hardware cost,conventional network architecture,power consumption,identified dominated flows,network performance,networks-on-chips,noc systems,network architectures,self-tuning network,regression analysis,statistical traffic prediction,self-tuning,traffic volumes,online learning,data traffics,network performance subject,proposed self-tuning network approach,capability,reconfigurable,complex run-time traffic patterns,regression,comprehensive noc simulators,analysis scheme,performance evaluation,dominated traffic flows,data traffic,design-time,critical pathways,new approach,network-on-chip,dominance data flows,large traffic volume,network design,pipelines,data models,benchmark testing,control systems,polynomials,predictive models,network on chip | Journal | 13 |
Issue | ISSN | Citations |
2s | 1539-9087 | 16 |
PageRank | References | Authors |
0.60 | 17 | 7 |
Name | Order | Citations | PageRank |
---|---|---|---|
Xiaohang Wang | 1 | 895 | 53.93 |
Mei Yang | 2 | 81 | 8.07 |
Yingtao Jiang | 3 | 492 | 60.58 |
Liu Peng | 4 | 71 | 6.17 |
Masoud Daneshtalab | 5 | 609 | 60.88 |
Maurizio Palesi | 6 | 1119 | 78.82 |
Terrence Mak | 7 | 73 | 6.87 |