Name
Abstract | ||
|---|---|---|
Efficient use of multiple functional units in superscalar processors requires instruction level parallelism to be detected and exploited. Thus special hardware in the form of dispatch units is used to uncover scheduling opportunities within an instruction window at run-time. Using the superscalar PowerPC 604 as an example we show that such processors still benefit from more broadly scoped scheduling at compile time. In our approach we reuse an existing retargetable VLIW compiler environment by instantiating it for a VLIW processor whose resources and instruction timings resemble those of the PowerPC. |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1007/BFb0026435 | Lecture Notes in Computer Science |
Keywords | Field | DocType |
vliw compilation techniques,superscalar architectures,computer architecture,compiler optimization,functional unit | Instruction-level parallelism,Computer architecture,Computer science,Compile time,Very long instruction word,Scheduling (computing),Parallel computing,Compiler,Optimizing compiler,Instruction window,PowerPC | Conference |
Volume | ISSN | ISBN |
1383 | 0302-9743 | 3-540-64304-4 |
Citations | PageRank | References |
5 | 0.64 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Esther Stümpel | 1 | 5 | 0.64 |
| Michael Thies | 2 | 84 | 10.01 |
| Uwe Kastens | 3 | 406 | 55.65 |