Name
Abstract | ||
|---|---|---|
Power consumption in a synchronous FSM (Finite-State Machine) can be reduced by partitioning it into a number of coupled sub-FSMs where only the part that is involved in a state transition is clocked. Automatic synthesis of a partitioned FSM includes a partitioning algorithm and sub-FSM synthesis to an implementation architecture. In this paper, we first introduce an implementation architecture for partitioned FSMs that uses gated-clock technique for disabling idle parts of the circuits and asynchronous controllers for communication between the sub-FSMs. We then describe a new transformation procedure for the sub-FSM. The FSM synthesis how has been automated in a prototype tool that accepts an FSM specification. The tool generates synthesizable RT-level VHDL code with identical cycle-to-cycle input/output behavior in accordance with the specification. An average power reduction of 45% has been obtained for a set standard FSM benchmarks. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1155/2001/27496 | VLSI DESIGN |
Keywords | Field | DocType |
low-power design,FSM decomposition,FSM partitioning,asynchronous logic,gated-clock techniques,RTL-synthesis | Asynchronous communication,Computer science,Idle,Real-time computing,Electronic engineering,VHDL,Electronic circuit,Power consumption,Embedded system | Journal |
Volume | Issue | ISSN |
12 | 2 | 1065-514X |
Citations | PageRank | References |
3 | 0.47 | 9 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| B Oelmann | 1 | 77 | 21.78 |
| Estonia Margus Kruus | 2 | 3 | 0.47 |
| Estonia Mattias O'Nils | 3 | 3 | 0.47 |
| Mattias O'nils | 4 | 121 | 26.67 |