Abstract | ||
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This paper presents a simulation model of the Time-Triggered Protocol (TTP/C) based embedded computer system as a tool for evaluation of system capability to tolerate a chosen category of faults. The model, being written in ANSI-C, is portable and machineindependent. Its structure is modular and flexible, so that the system to be studied and the experiment setting can easily be changed. The functionality of this model is demonstrated on a set of fault injection experiments aimed mainly to evaluate the correctness of the TTP/C specification. These experiments were done within the EU/IST FIT (Fault Injection for Time triggered architecture) project solution. |
Year | DOI | Venue |
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2002 | 10.1007/3-540-36080-8_23 | EDCC |
Keywords | Field | DocType |
fault injection,ist fit,chosen category,embedded computer system,system capability,simulation model,time-triggered protocol,c specification,fault injection experiment,experiment setting,model-based dependability evaluation method,embedded computing | Dependability,Computer science,Correctness,Real-time computing,Fault tolerance,Time-Triggered Protocol,Transmission protocol,Modular design,Time-triggered architecture,Fault injection,Distributed computing,Embedded system | Conference |
Volume | ISSN | ISBN |
2485 | 0302-9743 | 3-540-00012-7 |
Citations | PageRank | References |
3 | 0.55 | 7 |
Authors | ||
3 |
Name | Order | Citations | PageRank |
---|---|---|---|
Pavel Herout | 1 | 22 | 6.87 |
Stanislav Racek | 2 | 14 | 4.98 |
Jan Hlavicka | 3 | 83 | 12.76 |