Title
Synthesizing Hardware from Dataflow Programs - An MPEG-4 Simple Profile Decoder Case Study
Abstract
The MPEG Reconfigurable Video Coding working group is developing a new library-based process for building the reference codecs of future MPEG standards, which is based on dataflow and uses an actor language called Cal. The paper presents a code generator producing RTL targeting FPGAs for Cal, outlines its structure, and demonstrates its performance on an MPEG-4 Simple Profile decoder. The resulting implementation is smaller and faster than a comparable RTL reference design, and the second half of the paper discusses some of the reasons for this counter-intuitive result.
Year
DOI
Venue
2011
10.1007/s11265-009-0397-5
JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
Keywords
Field
DocType
Dataflow,CAL,Reconfigurable Video Coding,MPEG,High-level synthesis
Computer science,Real-time computing,Theoretical computer science,Dataflow,MPEG-4,Codec,Hardware description language,Parallel computing,High-level synthesis,Field-programmable gate array,Code generation,CAL Actor Language,Embedded system
Journal
Volume
Issue
ISSN
63
SP2
1939-8018
Citations 
PageRank 
References 
60
4.61
5
Authors
6
Name
Order
Citations
PageRank
Jörn W. Janneck166257.24
Ian D. Miller2938.44
David B. Parlour313811.66
Ghislain Roquier422119.57
Matthieu Wipliez524118.36
Mickaël Raulet637039.15