Name
Title | ||
|---|---|---|
Design of a 1.8V 8-bit 1GSPS cascaded-folding CMOS A/D converter based on a folder averaging technique |
Abstract | ||
|---|---|---|
In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18¿m 1-poly 5-metal CMOS technology. The active chip area is 0.72mm2 and it consumes about 200mW at 1.8V power supply. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/SOCCON.2009.5398092 | SoCC |
Keywords | Field | DocType |
cmos integrated circuits,self-linearized preamplifier,source degeneration,word length 8 bit,analogue-digital conversion,folder averaging,auto-switching encoder,preamplifiers,voltage 1.8 v,cmos a/d converter,size 0.18 mum,interpolation structure,1-poly 5-metal cmos technology,analog-to-digital converter,cascaded folding,signal to noise ratio,interpolation,chip,data mining,phase locked loops | Phase-locked loop,Preamplifier,Computer science,Interpolation,8-bit,CMOS,Chip,Analog-to-digital converter,Electronic engineering,Encoder | Conference |
ISBN | Citations | PageRank |
978-1-4244-4941-5 | 0 | 0.34 |
References | Authors | |
2 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dongheon Lee | 1 | 50 | 3.99 |
| Seunghun Kim | 2 | 31 | 6.05 |
| Jooho Hwang | 3 | 0 | 0.68 |
| Junho Moon | 4 | 4 | 3.00 |
| Minkyu Song | 5 | 32 | 15.30 |