Title
Power-efficient ASIC synthesis of cryptographic sboxes
Abstract
In this paper we present a novel methodology that can be used to design efficient hardware structures for a certain class of combinatorial functions. The methodology is primarily intended to achieve low-power synthesis of non-linear one-to-one functions on ASIC technology libraries and fits well for the synthesis of small cryptographic substitution box (Sbox) functional components; the latter are found in most secret key cryptographic algorithms, and usually represent their most relevant part in terms of required computational power. We also describe an extension that allows us to apply the method to general vectorial Boolean functions.
Year
DOI
Venue
2004
10.1145/988952.989019
ACM Great Lakes Symposium on VLSI
Keywords
Field
DocType
cryptographic sboxes,efficient hardware structure,novel methodology,low-power synthesis,general vectorial boolean function,power-efficient asic synthesis,functional component,certain class,combinatorial function,asic technology library,secret key cryptographic algorithm,small cryptographic substitution box,power efficiency,cryptography
Boolean function,Asic technology,Power efficient,Cryptographic protocol,Computer science,Cryptography,Application-specific integrated circuit,Cryptographic primitive,Electronic engineering,Theoretical computer science,Security of cryptographic hash functions
Conference
ISBN
Citations 
PageRank 
1-58113-853-9
22
1.20
References 
Authors
9
4
Name
Order
Citations
PageRank
Guido Bertoni169641.77
Marco Macchetti218616.54
Luca Negri3686.59
Pasqualina Fragneto413114.36